The expression (a.b)c' + (a.b')c + (a'.b)c was to be realised with 2-input AND gates and OR gates. However during realization all 2-input AND gates were mistakenly substituted by 2-input NAND gates. What is the function finally obtained ?

Concept:

The given Boolean expression is:

\( (a \cdot b)c' + (a \cdot b')c + (a' \cdot b)c \)

It was to be realized using AND and OR gates. But all 2-input AND gates were mistakenly replaced by 2-input NAND gates.

We need to determine the new expression with these incorrect gates.

Step-by-Step Evaluation:

Let’s denote the original terms:

T1 = \( (a \cdot b)c' \)

T2 = \( (a \cdot b')c \)

T3 = \( (a' \cdot b)c \)

Now, replacing each **AND** with **NAND**, each term becomes:

\( a \cdot b \rightarrow (a \cdot b)' \)

\( (a \cdot b)' \cdot c' \rightarrow ((a \cdot b)' \cdot c')' \) — since second AND also becomes NAND

Similarly for other terms:

\( ((a \cdot b')' \cdot c)' \) and \( ((a' \cdot b)' \cdot c)' \)

Each term is now a NAND of a NAND and a variable → effectively behaves like NOR logic and outputs tend to 1 for all combinations.

Let’s test values for all combinations of a, b, c (truth table) — we find that output is 1 for all cases due to the nature of NAND-ing every AND gate. The circuit effectively turns into one that always outputs logic high (1).