Sequential Circuits MCQ Quiz - Objective Question with Answer for Sequential Circuits - Download Free PDF

Concept:

A JK flip-flop toggles its output on every clock pulse when both J and K are high.

Given configuration:

• J = 1 (logic high)
• K = Q′ (complement of Q)

This means K will be 1 when Q is 0, and K will be 0 when Q is 1.

Initial Condition:

Q = 0 (flip-flop is initially cleared)

Apply 6 Clock Pulses:

Final Output Sequence at Q:

0 1 1 1 1 1 → 011111

Concept: 

JK flip flop:

The truth table of JK flipflop:

T flip-flop is formed by combining both J and K inputs of the JK-flipflop

In the above truth table when J = K = 1, its output is toggled.

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Characteristic Table of JK flip flop

Qn+1 = JQ̅n + K̅Qn

Explanation:

• Master-Slave flip-flop is the cascaded combination of two flip-flops among which the first is designated as master flip-flop while the next is called slave flip-flop.
• The master flip-flop is triggered by the external clock pulse train while the slave is activated at its inversion i.e. if the master is positive edge-triggered, then the slave is negative-edge triggered and vice-versa.
• There will be a change in the output when the state of the slave is affected because the output is taken at the slave.

Working:

The structure of the Master-slave JK flip flop is shown below

Working of Master-Slave flip flop

1) When CLK = High, the Master will be active and the slave will be inactive.

Feedback values don’t change as slave flip flop is inactive. Due to this Master output Toggles only once in one clock pulse.

2) When CLK = low

The latest master outputs are transferred to slave inputs and output is obtained. That is slave output change only once in one clock pulse.

3) Master-Slave JK flip flop is similar to the negative edge triggered flip flop

4) Master-Slave JK flip flop also can be converted to positive edge-triggered as shown

The correct statement about the behavior of a D Flip-Flop when the clock input is NOT transitioning is: 1) The output remains at the last value.

Explanation:

• Edge-Triggered Behavior: A D flip-flop is an edge-triggered device. This means it samples its input (D) and updates its output (Q) only at a specific transition of the clock signal (either the rising edge or the falling edge, depending on its design).

• Latched State: When the clock input is not transitioning (i.e., it's held high, held low, or in between edges), the flip-flop is in a latched state. In this state, its output is isolated from the D input. Any changes in the D input during this period will not affect the output. The output simply holds the data that was present at the last active clock edge.

Explanation:

JK Flip-Flop

Definition: A JK flip-flop is a type of digital storage element used in sequential logic circuits. It is named after its inventor, Jack Kilby. The JK flip-flop is a refinement of the SR flip-flop, where the indeterminate state (when both inputs are set to 1) is eliminated by toggling the output. It has two inputs, labeled J and K, and a clock input that controls the timing of state changes.

Working Principle: The JK flip-flop operates based on the values of its inputs (J and K) and the current state of the output (Q). On the rising or falling edge of the clock signal (depending on the flip-flop's configuration), the output state changes according to the following truth table:

Truth Table of J-K flip flop

At J = 0, K = 0, the J-K flip flop has no changes in the next state from the present state.

Truth Table of S-R flip flop

Truth Table of D flip flop

Truth Table of T flip flop

D flip flop:

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Q_n+1 = D

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

The D flip flop may be obtained from a J-K flip flop by just putting one inverter between the J and K as shown in the figure below.

K = J̅

T flip flop:

T flip flop has only one input terminal. The output of the T flip flop will be toggled when the input is high on every new clock pulse. The output will be the same as the previous state when the input is low.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Q_n+1 = TQ̅­_n + T̅Q_n

The T flip flop may be obtained from a J-K flip flop by making both the inputs are the same i.e. J = K.

Flip-Flop

• A flip-flop is the basic storage element in sequential logic.
• A flip-flop is a device that stores a single bit (binary digit) of data.
• The stored data can be changed by applying varying inputs.
• Flip Flops are edge-triggered while the latch is level-triggered.
• Flip Flops are of 4 types: SR, JK, T, and D flip-flops.

​Register

• A Register is a collection of flip-flops.
• For storing n-bit data, a register comprising of n number of flip-flops is used.

GATE

• A logic gate is a device that acts as a building block for digital circuits.
• They perform basic logical functions that are fundamental to digital circuits. 
• Example: AND, OR, NOT, NAND, NOR, XOR, XNOR

Race around condition:

For JK flip-flop if J, K, and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition.

This can be eliminated by using the following methods.

• Increasing the delay of flip-flop
• Use of edge-triggered flip-flop
• Use of master-slave JK flip flop

The Master-slave configuration is used in a flipflop to eliminate the race around condition but not to store two bits of information.

Explanation:

1. Practically, we don’t get toggling in sequential circuits. Since clock pulse is more than the propagation delay, so within one clock pulse the output will keep on toggling again and again and it may become indeterminate. This is known as the race-around condition.

2. Race Around condition occurs because of the feedback connection.

Race around condition (RAC)

• Race around condition occurs only in level-triggered flip flop
• Level triggered is transparent.
• Even though input is constant, output continuously toggles. Changes for some time continuously.

• RAC is when J = 1 and K = 1 [flip flop in toggling mode] and tp > tff
• Output toggles many times instead of once in one clock pulse. It is undesirable and called as “Race Around Condition”

Race around condition can further be explained with SR latch example:

A clocked latch is shown below

• When S = R = CLK = 1
• The outputs Q and Q’ are maintained at logic 0
• There is no race around condition

• However, when clocked SR latch is converted to JK flip flop by providing feedback as shown below

• Then when J = K = CLK = 1, then the output Q and Q’ keeps toggling between 0 and 1, thus, there is a race around condition there

So we can conclude that racing condition occurs in sequential circuits with the level-triggered clock.

Hence option (2) is the correct answer.

Important Points

The race around condition can be eliminated by using the following methods:

• Increasing the delay of flip-flop
• Use of edge-triggered flip-flop
• Use of master-slave JK flip flop

The Master-slave configuration is used in a flipflop to eliminate the race-around condition but not to store two bits of information.

D flip flop :

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

∴ The one input RS flip flop is the D flip flop.

The correct answer is option 1): Counter

Concept:

• Flip-flop is a 1-bit memory cell which can be used for storing digital data.
• To increase the storage capacity in terms of the number of bits. A group of flip-flops is used. Such a group of flip-flops is known as a Register.
• A register capable of incrementing and/or decrementing its contents is called a counter
• A counter is a register capable of counting the number of clock pulses arriving at its clock input.
• A register is a group of flip-flops used to store multiple bits of data. An adder is a digital logic circuit in electronics that is extensively used for the addition of numbers.
• A latch is a circuit that has two stable states and can be used to store state information.
• The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.

Concept:

Shifting a register content to left by one bit is equivalent to multiplication by 2.

Shifting a register content to right by one bit is equivalent to division by 2.

Explanation:

The PRESET and CLEAR inputs of the JK Flip-Flop are asynchronous, which means that they will have an immediate effect on the Q and Q’ outputs regardless of the state of the clock and / or the J and K inputs.

1.When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock.

 2.When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.

3.When preset and clear inputs are activated we get an invalid state on the output, where Q and not-Q go to the same state.

Important Points-

JK Flip-Flop Truth Table- From  truth table it can be seen that the CLEAR (CLR) and PRESET inputs are active at a low logic level  and put on the Q output of the Flip-Flop, a high logic level regardless of the state of the clock and / or the state of the J and K inputs.

Concept:

In Ripple counters, the carry ripples through, or propagates through every flip-flop, i.e. the propagation delays of all the flip-flops are added to get the overall delay in the counter.

For the counter to work properly, the next clock pulse must arrive when all the carry's generated are propagated through all the flip-flops and the output is stable. This can be mathematically stated as:

For the ripple counter to count properly:

T_CLK ≥ n (t_pd)_FF

T_CLK = Clock Interval, and is the inverse of f_CLK, i.e.

\(f_{CLK}≤ \frac{1}{n\times (t_{pd})_{FF}}\)

Calculation:

For 4-bit modulo 16 ripple counter has 4 JK flip flops. The total propagation delay will be:

\(T = 4 \times 50\;n\;sec \)

T = 200 nsec

∴ The maximum clock frequency will be:

\(f = \frac{1}{{200\;n}} = 5\;MHz\)